Study of resistivity and electromigration behaviour in interconnections intended for the 90 nm - 32 nm node technologies

Jean-Frédéric Guillaumond
Language of the thesis
Thesis name in original language
Etude de la r´esistivit´e et de l’´electromigration dans ´ lesinterconnexions destin´ees aux technologies des noeuds 90 nm - 32 nm
Abstract & Cover

One of the major challenges of the next generations of integrated circuits concerns interconnections. The copper lines connecting the active components will delimit the performance and reliability of future microprocessors. The performance of the interconnects depends on the effective resistivity of the metallic line and the dielectric coefficient of the interline insulation. To increase performance, new low permittivity insulators and reduced thickness diffusion barriers are introduced. In addition, the reduction in dimensions leads to a modification of the resistivity of the copper and an increase in the current density. The objective of this thesis was to analyze this increase in resistivity and to deepen the knowledge of electromigration in the lines of interconnections in which these new materials are integrated. On the one hand, a very detailed study of the increase in resistivity in copper when the minimum dimensions of the lines become of the same order of magnitude as the mean free path of the electron has been carried out. A model based on the work of [Mayadas and Shatzkes, 1970] has been proposed. The increase in resistivity is explained on the one hand by a diffusion of electrons at the grain boundaries of copper, a first parameter (1-Rm) is introduced corresponding to the probability of passage of the electron at the grain boundaries and on the other hand by a diffusion of electrons on the walls of lines. A second parameter p corresponding to the probability of elastic reflection of the electron on the walls accounts for this phenomenon. The electrical characterization of lines with a width of less than 50 nm was carried out using a method of electrical extraction of the resistivity and the surface of copper. The uncertainty on the values obtained was estimated. We have indeed observed an increase in resistivity. The Mayadas model makes it possible to correctly model the experimental data. On the other hand, we have shown that the two electron scattering mechanisms have the same width dependence and we have mentioned the difficulty of differentiating between the two mechanisms. Complementary studies will have to be carried out to characterize the two phenomena more finely: measurement of grain size, variation in the thickness of the lines with more or less long CMPs, measurement of the roughness of the flanks by AFM, etc. On the other hand, a global study of electromigration in the interconnections of the next generations of interconnection has been carried out. The interpretation of the results was accomplished using the modeling of [Korhonen et al., 1993]. This takes into account the confinement of copper in the phenomenon of diffusion of the metal under the effect of a "wind" of electrons via an effective modulus B. This modulus was determined for our geometries of line and for our material parameters thanks to the CASTEM finite element software. Classical electromigration studies (temperature and current stress, post-mortem SEM observation) have enabled us to extract the electromigration behavior of new materials used to increase the electrical performance of interconnect lines. We first observed a decrease in electromigration performance with the use of a porous dielectric. The properties of this material are a low electric permittivity in order to decrease the interline coupling and a low Young's modulus due to the presence of porosity in the dielectric. The simulation of B shows a reduction in the effective modulus with the use of this material. The analytical solutions of the Korhonen model then indicate an increase in lifetime for a lifetime limited by the nucleation of a cavity and a decrease in lifetime in the case of a lifetime limited by the growth of a cavity. Our experimental results indicate an activation energy identical to that obtained with a dense insulator indicating an identical diffusion site in both cases but a lifetime one decade lower in the case of the porous material. The lifespan therefore seems to be limited by the growth of a cavity. The interpolations to the operating conditions indicate that the porous material does not meet the requirements of the 65 nm node in terms of reliability. The impact of the diffusion barrier (PVD TaN/Ta, ALD TaN, CVD TiN) was determined. An almost similar activation energy is observed for each variant possessing a TaN/Ta PVD barrier (about 0.8 eV). On the other hand, an increase in the dispersion of the results is obtained by reducing the thickness of the line and a reduction in the dispersion by carrying out an H2 plasma before deposition of the barrier. The activation energy obtained for the TiN barrier is lower (0.62 eV) and the dispersion of the results greater than in the case of a TaN/Ta barrier. It is difficult to interpret this activation energy and we believe that this energy reduction may be related to a non-optimized copper deposition (CVD). On the other hand, a lifespan is observed under test conditions that are much longer than the PVD TaN/Ta barrier. This result could be related to the greater thickness of the TiN CVD barrier and therefore a higher copper confinement. The ALD barrier has the thinnest barrier width (3.5 nm) and therefore the lowest effective resistivity. From the electromigration point of view, we observe a multimodal behavior of the fractures which prevents us from correctly extracting an activation energy. By carrying out extrapolations to operating conditions, we show that none of these three barriers makes it possible to obtain the desired performance with a porous dielectric for the 65 nm node. We then showed the impact of the upper corner of copper lines on electromigration using new morphological characterizations: in situ SEM and EBSD. The first makes it possible to follow the evolution in real time of the growth of a cavity while the second makes it possible to correlate the presence of a cavity with the crystalline orientations on either side of the cavity. We have thus shown that cavity nucleation is favored at the intersection of a grain boundary and the diffusion barrier. We could not conclude on the presence of a crystalline orientation favoring electromigration. The reduction in the dimensions of the lines does not lead to a marked drop in lifetimes, but an increase in the dispersion of breaks is observed. New processes have been evaluated with the aim of improving the electromigration behavior of interconnects. The use of copper alloy made it possible to obtain a higher activation energy (1.3 eV), but in return a higher resistivity of the copper was measured. Different self-positioned metallic barrier deposition processes allowing to reduce the interline capacitance have been evaluated. These metal upper barriers have made it possible to significantly improve electromigration performance. An activation energy close to the theoretical value of solid copper was obtained, meaning a complete blockage of the diffusion paths at the interfaces. The phenomenon of electromigration at the operating conditions of the integrated circuits is then almost nil. On the other hand, the presence of a metal barrier is not a sufficient condition to obtain such performance. We also note a possible increase in the resistivity of the copper by diffusion of the elements of the barrier in the copper matrix. These studies were conducted on single level structures. To complete it, it is necessary to qualify double-level structures, one of the particularities of which is the presence of a diffusion barrier at the bottom of the via. In situ SEM characterization can be coupled with EBSD analysis and conducted on narrower line widths. The metal barriers seem very promising and additional studies will have to be carried out with in particular more statistics and characterizations of the post mortem defects.

Laboratoire d'Electronique et des Technologies de l'Information
(Grenoble, France)
External Link
Read Thesis
linkedin invite