Novel concepts for advanced CMOS: Materials, process and device architecture

Author
Dongping Wu
Year
2004
Abstract & Cover

The continuous and aggressive dimensional miniaturization of the conventional complementary-metal-oxide semiconductor (CMOS) architecture has been the main impetus for the vast growth of IC industry over the past decades. As the CMOS downscaling approaches the fundamental limits, unconventional materials and novel device architectures are required in order to guarantee the ultimate scaling in device dimensions and maintain the performance gain expected from the scaling. This thesis investigates both unconventional materials for the gate stack and the channel and a novel notched-gate device architecture, with the emphasis on the challenging issues in process integration. High-κ gate dielectrics will become indispensable for CMOS technology beyond the 65-nm technology node in order to achieve a small equivalent oxide thickness (EOT) while maintaining a low gate leakage current. HfO2 and Al2O3 as well as their mixtures are investigated as substitutes for the traditionally used SiO2 in our MOS transistors. These high-κ films are deposited by means of atomic layer deposition (ALD) for an excellent control of film composition, thickness, uniformity and conformality. Surface treatments prior to ALD are found to have a crucial influence on the growth of the high-κ dielectrics and the performance of the resultant transistors. Alternative gate materials such as TiN and poly-SiGe are also studied. The challenging issues encountered in process integration of the TiN or poly-SiGe with the high-κ are further elaborated. Transistors with TiN or poly-SiGe/high-κ gate stack are successfully fabricated and characterized. Furthermore, proof-of-concept strained-SiGe surface-channel pMOSFETs with ALD high-κ dielectrics are demonstrated. The pMOSFETs with a strained SiGe channel exhibit a higher hole mobility than the universal hole mobility in Si. A new procedure for extraction of carrier mobility in the presence of a high density of interface states found in MOSFETs with high-κ dielectrics is developed. A notched-gate architecture aiming at reducing the parasitic capacitance of a MOSFET is studied. The notched gate is usually referred to as a local thickness increase of the gate dielectric at the feet of the gate above the source/drain extensions. Two dimensional simulations are carried out to investigate the influence of the notched gate on the static and dynamic characteristics of MOSFETs. MOSFETs with optimized notch profile exhibit a substantial enhancement in the dynamic characteristics with a negligible effect on the static characteristics. Notched-gate MOSFETs are also experimentally implemented with the integration of a high-κ gate dielectric and a poly-SiGe/TiN bi-layer gate electrode.

Source of Information
Jonas Sundqvist
University
Royal Institute of Technology (KTH), Department of Microelectronics and Information Technology (IMIT)
(Stockholm, Sweden)
External Link
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