A study on SrTiO3 thin films deposited by plasma-enhanced atomic layer deposition for DRAM capacitor dielectric

Ji-Hoon Ahn
Abstract & Cover

The downscaling of the DRAM device is necessary to achieve higher speed with less power consumption. It is getting difficult to meet the new requirements with the existing SiO2 or Si3N4 due to their low dielectric constants and tunneling leakage currents through the thin layers. For this reason, high-k materials enabling high-k and low leakage currents with physically thicker film have received considerable attention. Among the candidate for DRAM capacitor dielectrics, SrTiO3 is a promising candidate for giga-bit scale dynamic random access memory (DRAM) capacitors because of its high dielectric constant, high breakdown strength and good thermal stability.

SrTiO3 films were deposited on 20 nm-Ru/25 nm-TiN/p-type Si (100) substrates by plasma-enhanced atomic layer deposition at a deposition temperature of 225oC and a deposition pressure of 3 Torr using 0.2M Sr(DPM)2 dissolved in butyl acetate and TTIP as precursors and O2 plasma as an oxidant.

SrO and TiO2 films were grown separately to investigate the ALD characteristics. The thickness per cycle of SrO and TiO2 are saturated to 0.054 nm/cycle 0.036 nm/cycle at 225, respectively. The composition of STO films was controlled by changing the number of each precursor cycles, and stoichiometric SrTiO3 films were obtained when one super-cycle consisted of six TiO2 cycles and seven SrO cycles.

The deposited-SrTiO3 films were crystallized after annealing at 600oC for 10min under N2 ambient and the dependence of the dielectric constant on SrTiO3 film thickness was investigated for less 50 nm-thick SrTiO3 films after the annealing process at 600oC for 10min under N2 ambient. The dielectric constants of the films having thickness higher than 20 nm were not as sensitive to the film thickness with a relatively constant value of about 65. However, the dielectric constants of the films with thickness under 15 nm were dramatically decreased with decreasing the film thickness. This change was related to the film crystallinity. Moreover, it was confirmed that non-stoichiometric region near the interface of SrTiO3 film and Ru bottom electrode existed and was intermixed with SrTiO3 and Ti-O phases. The dielectric constant of only SrTiO3 film being excluded the interface layer was about 85. As the crystallization of deposited-SrTiO3 film by annealing at 600 for 10min in ambient N2, the leakage current density abruptly increased from the level of 10-7~10-8 at ±1V to the level of 10-1~10-2 at ±1V owing to formation of the grain boundary as the leakage current path, irrespective of the film thickness.

To improve dielectric properties, crystallization the seed-layer was introduced. First, seed layer was prepared by depositing 2.7-nm SrO and post-annealing in ambient N2 at 600°C for 10min before SrTiO3 deposition. By inserting of the SRO seed-layer between the SrTiO3 thin film and the Ru bottom electrode, the crystallinities of the annealed-SrTiO3 films were enhanced, especially film thickness with below 15 nm. In aspect of dielectric properties, SRO seed-layer helped to increase the dielectric constant of the SrTiO films, especially films with thicknesses below 15 nm (3the dielectric constant of 10 nm-SrTiO3 films was increased from 15.7 to 50.3) and the thickness dependency of the dielectric constant was reduced. Moreover, it was confirmed that the low-k interfacial layer between SrTiO film and bottom electrode was reduced by inserting of the seed-layer. For optimization of SRO seed layer formation, the dependence of dielectric properties of SrTiO films on the thickness of the inserted SrO layer was investigated. 33As the SrO layer was reduced below 1.35 nm, the dielectric constants of the SrTiO3 films drastically decreased and the dielectric constants of SrTiO3 thin films decreased continuously as the thickness of the inserted SrO layer was increased beyond 1.35 nm. From the above results, it appears that the optimized thickness of the inserted SrO layer for forming a seed layer is 1.35 nm, at which had the highest dielectric constant.

If the RuO2 layer was used as the substrate instead of Ru, it was thought that the sufficient oxygen supply might be possible for transformation of deposited-SrO to the SrRuO3 layer (SrO + RuO2 → SrRuO3) and the O2 ambient annealing could be possible as well as N2 ambient annealing for crystallization of SrTiO3 thin films. Therefore, SrRuO3 was introduced as a crystallization seed layer and formed through deposition of a SrO layer on a RuO2 substrate followed by O2-annealing instead of on a Ru substrate followed by N2-annealing, as the second method for seed layer formation. The SrRuO3 layer was successfully formed after annealing of a 2.7-nm SrO/RuO2 sample at 600°C. As the results of introducing SrRuO seed layers, 3the dielectric constant of 10 nm-thick SrTiO3 thin films increased to 83 compared with films deposited on Ru directly and seed formed on Ru substrate, respectively.

Finally, the effect of alumina (Al2O3) insertion on electrical properties of SrTiO3 was investigated. To investigate the variation of electrical properties of Al2O3-added SrTiO3 films, the added Al2O3 were inserted in SrTiO3 thin films by two different ways. The first method for reducing leakage current by addition AlOto SrTiO films is the doping of AlO in SrTiO thin film and the second method is the insertion of nano-scale-thick AlO layer in SrTiO thin film as the leakage current blocking layer. In the case of SrTiO film deposited on SrRuO seed layer formed on RuO substrate, the best optimized condition was obtained by 23 3233233332insertion of Al2O3 layer with 10 cycles (corresponding thickness of about 1.2 nm) and in this case, the leakage current density at 1V and dielectric constant were 9x10-7 A/cm3 and 53, respectively.

Source of Information
Minsung Kim
Korea Advanced Institute of Science and Technology
(Daejeon, Republic of Korea)
Other notes
Thesis kindly supplied by Ji-Hoon Ahn
External Link
Read Thesis
linkedin invite