Scaling Mount Nano: ALD for 3D integrated circuits in your phone

This article has been written by Jesse Kalliomäki and Ilkka Manninen.

Picosun - An Applied Materials Company

The silicon heart

Few objects can embody our current age like electronics. More specifically, the electronic circuitry found in our phones. Modern smartphones have permeated and infiltrated nearly every level of our social and personal life. It is the only device you are likely to carry with you everywhere you go. And the computer embedded in the phone allows you to work on the go while waiting for a bus, and then procrastinate in the office by watching the latest cat videos. In fact, just existing in an urban environment is rather difficult without the phone nowadays, as it lets you interface with the rapidly developing Internet-of-Things. 

Truly Ångström

The reason the phone has been able to transform our lives is due to the heart ticking inside its plastic shell. Within that shell lies a computer consisting of many parts, including microchips, or just “chips” in short (Fig. 1a–b).  These processor and memory chips are powerful miniaturized electronic circuitries, programmed to process data and communicate with other devices to provide us live communication and access to service with speed and efficiency that would have seemed like magic just a couple decades ago. How these chips get made is another kind of magic in itself, called semiconductor device fabrication. An art and science so secretive and sought after it is considered a matter of national security. The process of making the ever-so-important chips is getting harder each year as the fabricated features get more intricate, with lithography now at 3 nm and  2 nm in 2025, reaching true Ångström dimensions.

DIY microchips

The fabrication process starts with a round piece of shiny and glass-like semiconductor material (traditionally a silicon wafer (Si)) (Fig. 1c) and ends up with a colourful round piece of semiconductor material, with instructions to interface with the world etched into its structure (Fig. 1d). This fabrication process consists of series of steps of coating (deposit), patterning (lithography) and removing (etch) thin film materials. These steps add, shape or remove film material anywhere between 1 to 100 000 nanometers. Developing and optimizing techniques to complete these steps is a subject of shelf-kilometers worth of scientific literature. The rest of this article will delve deeper into the deposition processes used in the fabrication process, and why 3D uniform coating of ALD makes it unique and necessary for these chips to be made.

The deposition processes toolbox has choices like chemical and thermal oxidation, physical vapour deposition (PVD) and chemical vapour deposition (CVD). Each of these technologies is suitable for specialized tasks with their own strengths and weaknesses. 
 

Figure 1: a) A clean 300 mm Si wafer. b) 300 mm device wafer undergone semiconductor fabrication process. c) Complete individual microchip being tested. d) A chip integrated into a circuit board assembly. 

For example, if the device needs an insulating thin film, like silicon dioxide (SiO₂) layer on an exposed Si surface, it can be rapidly accomplished by thermal oxidation. In thermal oxidation, the sample is subjected to temperatures often in excess of 1000°C in the presence of oxidative chemicals. This environment converts the surface of exposed Si into SiO₂, creating a high-quality thin film with properties different from the original surface. However, this is only viable if there is the right type of surface available, as the film is always a product of the surface and the environment it is exposed to. A process analogous of rust forming on iron, or ice growing on water during a cold winter night.  

If the right surface is not readily available, experienced engineers are unfazed, as a new kind of surface can always be deposited using PVD or CVD. In the case of PVD, thin film is deposited by vaporizing (evaporating or sputtering) a target material and transporting it onto a substrate in ultra-high vacuum, where it condenses into a thin film. CVD techniques on the other hand rely on precursor chemicals introduced into a chamber with the substrate, where the film is the product of the chemical reactions and is coated over the substrate. Advantages gained from using these techniques are that they are significantly less dependent on the substrate and the deposited film can be carefully selected and the composition tuned. Nevertheless, the disadvantages are to be considered as well. PVD techniques are practically a line-of-sight deposition methods, and most CVD techniques are as well struggling with complex shaped substrates and risk leaving vital areas uncoated (Fig. 2).¹ More conventional CVD depositions also take place at high temperatures, or risk contaminating the sample with particles. 

One sub-class of CVD does a sublime job countering some of the downsides of the previous deposition techniques. As a CVD-technique, Atomic Layer Deposition (ALD) depends on chemical reactions to form a thin film. But in ALD, the precursor chemicals are introduced sequentially, and exclusively react with the original surface. Additional advantages this brings are that the film thickness can be controlled with unparalleled accuracy and since the reactions are limited to surface, the original shape and form are preserved. This is incredibly valuable as the fabricated features and circuitry have become more extreme with smaller dimensions, as the trend has been so far.

Figure 2: An illustration outlining how different deposition techniques are affected by high aspect ratio features. 

Climbing over the quantum wall

“Like there is a maximum limit of chip size, there is a minimum limit for traditional transistor”

Since the first chips were developed, the drive has been to give them higher performance. A way to accomplish that is to have a greater number of transistors on a chip. As there is a limit on the size of a useful chip, the straightforward way is to shrink the transistor size. And since the late 70’s, the transistor density on a chip has roughly doubled every two years, a trend called “Moore’s law”. The transistor shrinking also leads to a reduced power use per transistor. Imec in Belgium discussed 5 scaling walls:  memory, power, sustainability and cost walls. 

Regarding the quantum wall, like there is a maximum limit of chip size, there is a minimum limit for traditional transistor. Straight-up miniaturization of devices started to be unfeasible after certain dimensions in the devices were shrunk to the range of nanometers. Even though the fabrication method allowed to make devices so small, their functionality was compromised due to quantum phenomena like electrons tunneling through materials classically considered as insulators. This required innovations in materials research to prop up the trend, but the fact remained that 2D planes have only a finite size. The real gamechanger came when the limitations were circumvented by incorporating the 3^rd dimension into chip designs (Fig. 3).²
 

Figure 3: Vertical device architecture decreases the footprint of devices greatly, but also increases the aspect ratio of many processing steps. A beautiful visual presentation of a 3D NAND  non-volatile memory as used as flash memory in our phones, can be found in YouTube video.  Great X-ray images of 3D chips can be found here.

Once manufacturers started to build devices like non-volatile flash memory storage components incorporating NOT-AND logic gates (NAND) in vertical orientation instead of horizontal, the same chip real estate could be used more efficiently to increase chip performance. Implication being that a computer of same size could retain exponentially more information. Making it even better at computing.

Whole chips could also be combined on top of each other, connected by channels going through the semiconductor substrates (called Through Silicon Via, or TSV), combining functionalities of multiple chips with a footprint of one (Fig 4a), collectively called “advanced packaging” in 2.5 or 3D. 

This development also introduced difficulties in fabrication process. As the devices grew in 3^rd dimension, they got more complex in shape. TSVs can have aspect ratio (ratio of feature’s depth and opening) in range of 20–40 ³ and may need a thin and conformal coating lining the via to be a seed layer for subsequent Cu electroplating to complete the connection through the wafer (Fig 4a). Though higher aspect ratios (HAR) are encountered in applications such as advanced 3D NANDs boasting 232 layers of devices⁴ and having aspect ratios in excess of 100, or in the supercapacitors of the chip’s electrodes (Fig. 4b)⁵. The versatility of ALD also drives innovation in more classic device structures, as exemplified by Gate-All-Around (GAA) architecture, an evolution of a classic metal oxide semiconductor field effect transistor (MOSFET) used since the early days of computers. As mentioned previously, fabrication techniques based on PVD and CVD are not well suited for complex substrates. This is the area where ALD’s inherent compatibility with HAR outweighs its weaknesses and can be used to great effect to enable advanced chip production.

Figure 4: a) Series of adapted figures illustrating how ALD plays key role in 3D advanced packaging. b) A schematic of a capacitator with HAR features.⁵ c) A schematic of Gate-All-Around field effect transistor.

Square ALD in round trench

Making ALD processes work on a demanding 3D substrate, even with the advantage of conformal growth, is not easy and requires considerable efforts to make it work as intended. Firstly, not all ALD processes are made equal. There is a delightfully versatile roster of ALD's subclasses with varying methods to supply chemical reactions with energy and precursors. Transporting the precursor chemicals into small features happens mainly through diffusion, which does take time. Occasionally, the diffusion time can range from few seconds up to several minutes. Hence, the precursor chemicals must be selected with care and made sure they are fit for the journey by remaining stable for the duration of diffusion. 

This is rarely an issue with precursor chemicals used in thermal ALD processes like water, or most metal-organic precursors used responsibly. One notable exception is ozone, which has low half-life at high temperatures and converts into inert oxygen species in HAR structures.⁶ 

The issue realizes to much greater extent when one or more precursors are plasmas in plasma enhanced ALD (PEALD). The precursors only remain reactive when it exists as, which usually have short half-lives and may recombine and lose reactivity easily in collisions with surface.  Odds of recombination increases exponentially when the aspect ratio increases, as collisions may happen hundreds of times during diffusion into a small crevice or a long via. If precursors are lost during the diffusion process, the effective dose decreases, leaving the surface undersaturated. This leads to lackluster conformality of the resulting film and may cause the device to fail. However, with careful tuning of process conditions, PEALD processes can achieve impressively conformal growth as seen in Figure 5.
 

Figure 5: Highly conformal alternating layers of Al₂O₃, SiO₂ and TiO₂ deposited HAR structure with PE-ALD processes.

Two lessons ought to be learned from above brief examples. First is that the kind of ALD must be fit for purpose. PEALD offers versatility in for moderate aspect ratio, but for more extreme cases, good-old classic thermal ALD preferable. Second is precursor dose is optimized for the  HAR structure. Flat surfaces saturate faster and if one relies only on tests made on such samples, the pulse length will be too short and the driving force for diffusion is eliminated prematurely (Fig. 6).

Figure 6: When precursor pulses, with a fixed amount of chemicals, optimized for flat surfaces (AR=0) are used on high aspect ratio (HAR) structures, unexposed surfaces are left uncoated. This is true even if there are no added surface area.   

Effective experiments with HAR structures

We have seen that 3D high aspect ratio (HAR) structures are extremely important for creating higher performance computer chips, be it processors or memory chips. Without the unique nanoscale high aspect ratio conformal deposition of ALD, the performance and low energy use of today’s chips are not even possible. 

“ A lesson ALD scientists learn early on is that gases are lazy and will stubbornly avoid entering high aspect ratio cavities

In serious mass production of computer chips, up to 50 wafers of 300 mm each (about a size of vinyl records) are stacked in a cassette, with gaps of less than 1 cm. This open cassette is put inside a batch ALD reactor, and 50 wafers can be coated uniformly at once! However, a lesson ALD scientists learn early on is that gases are lazy and will stubbornly avoid entering HAR structures. Which means it takes time for the precursors to diffuse between the wafers, and obviously, we want to minimize the ALD cycle times to get the fastest throughput. These stacked wafers also form high aspect ratio structures, but on a macro-scale! 

So, to create fast, uniform deposition both inside nanoscale trenches, holes, vias, etc, and between larger wafers with small spacings, the cycle times must be optimized such that the reactants just reach (and get out) the bottom of trenches or penetrate stacked wafers. 

With nanostructures, it is possible to study coating thicknesses with cross-section Transmission Electron Microscope (TEM), but it is extremely time consuming and expensive. 

Ilkka Manninen and Jesse Kalliomäki at Picosun, an Applied Materials Company have discovered that it is possible to make a reusable, larger scale test structure, that also predicts well how uniform nanoscale HAR structures will be coated. ⁷

Our idea was to cover a silicon wafer with a metal disc with radial grooves (Fig. 7a). The height of each groove is different, ranging from several microns to few mm. When this plate is placed on top of a silicon wafer, it creates radial tunnels, through which the ALD precursor vapors need to diffuse. The smaller the height in the tunnel, the longer it takes for precursors to reach the (closed) end. When the cycle times are short, the precursors will not even reach the end of a thin tunnel. The result of a deposition is that thin tunnels produce a short arm, and tunnels with more internal height produce longer arms (Fig. 7c). The interesting part here is that this test method is easily measured even by eye, but can predict conformality of nanoscale HAR structures! 
 

Figure 7: Testing how deep an ALD coating uniformly coats a high aspect ratio (HAR) cavity. a) Flip side of the HAR test disk's cover, featuring the tunnel grooves radially extending from the central opening. b) An image how a resulting Si wafer looks like after a deposition. 

In summary

These are just a few ways how ALD’s application in high aspect ratio structures enable and enhance the chip making process, which is essential for modern phones. ALD has been a staple of the microelectronics industry since mid-2000’s and the trend with increased 3D vertical integration of devices and chips is only increasing. Enabling the industry by supplying tools to decrease trial-and-error experiments for HAR structures will help save resources down the line and further accelerate adoption of more ALD steps in chip fabrication. This means that the number of ALD layers in your phone is only about to increase in the future, continuing the trend of miracles from your cherished device.    

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Sources 

[1] Karsten Arts et al 2022 Plasma Sources Sci. Technol. 31 103002. DOI 10.1088/1361-6595/ac95bc
[2] Rong Chen et al 2020 Int. J. Extrem. Manuf. 2 022002. DOI 10.1088/2631-7990/ab83e0
[3] Fabien Piallat et al. J. Vac. Sci. Technol. B, 34, 021202 (2016); https://doi.org/10.1116/1.4942497 
[4] https://investors.micron.com/news-releases/news-release-details/micron-ships-worlds-first-232-layer-nand-extends-technology, accessed December 2022
[5] Shim et al. J. Mater. Chem. C, 2017, 5, 8000-8013
[6] Harm Knoops et al. Chem. Mater. 2011, 23, 2381–2387 DOI 10.1021/cm2001144

[7] (Patent application FI 20225248)
[Honourable mention] https://www.atomiclimits.com/

Further reading about HAR test structures

•  Jolien Dendooven et al 2009 J. Electrochem. Soc. 156 P63
• https://www.emdgroup.com/business-specifics/performance-materials/Semiconductors/us/ald-2020/Mechanism-of-Leakage-Variation-with-Aspect-Ratio-in-ALD-High-k-ZrO2-and-HZO-Dielectrics_AA-TuP70.pdf
• http://pillarhall.com/description.htm